1. Field
The following relates to integrated circuitry, and more particularly, to Single Event Effect (“SEE”) hardened circuitry for use with integrated circuitry, such as data storage circuitry. The following is directed toward reducing and/or eliminating the sensitivity of logic circuitry to SEE conditions, and to increasing the immunity of the logic circuitry to undershoot and/or overshoot conditions.
2. Related Art
Integrated circuits used in devices that operate in intergalactic space, earth orbital space, and high atmospheric altitudes (e.g., commercial flight altitudes) generally have to be highly reliable and operate using very low levels of power. Along with these necessities, space, weight and cost limitations generally cause these integrated circuits to be very densely populated and highly complex.
As a consequence of operating in intergalactic space, earth orbital space, and high atmospheric altitudes, however, the integrated circuits are exposed to a large amount of radiation, which can effect their operation and, in turn, their reliability. Because the Earth's magnetic field deflects most outer space radiation, terrestrial-based integrated circuits are not normally exposed to large amounts of radiation. Recently, however, several radiation-laden atmospheric storms, which emanated from a coronal mass ejection of the sun, expanded into space, penetrated the Earth's magnetic field, and disrupted a significant amount of terrestrial-based devices that use integrated circuits.
The disruptions caused by the radiation events are believed to result from Alpha particles (hereinafter “radiation particles”) interacting with the semiconductor materials (e.g., silicon) that make up the integrated circuits. These radiation particles are by-products of the natural decay of elements, and/or energetic protons, neutrons, electrons, and all the natural elements. The radiation particles are abundant in a wide range of energies in intergalactic space, earth orbital space, high atmospheric altitudes (e.g., commercial flight altitudes), and, as noted above, terrestrial space.
When a radiation particle interferes with an integrated circuit, it can slow the circuit's performance and even upset circuit operation. For example, a radiation particle can change the conductance of a metal-oxide-semiconductor (“MOS”) transistor by changing its threshold voltage Vt). In Very Large Scale Integration (VLSI) circuits, radiation particles can also generate significant transient voltage and current disturbances on internal (e.g. power and ground) nodes.
A radiation particle striking and passing through the structure of a transistor (or any semiconductor device) creates hole-electron pair separation along its path or “track.” The electrons separated by the radiation particle will migrate towards a high-voltage-state node of the transistor, resulting in a discharging current on the high-voltage node. If the discharging current exceeds, for example, the current holding the high-voltage state on the node, then the high-voltage-state node will transition to an undesired low state. Similarly, holes will migrate towards a low-voltage-state node of the transistor, resulting in a charging current on that node. If the charging current exceeds the current holding the low-voltage state on that node, then the low-voltage-state node will transition to an undesired high state. The result of the flip-flopping of the states of the high-voltage-state and low-voltage-state nodes is that an output of the transistor, and in turn, a larger system into which the transistor is integrated (e.g., a logic gate) may undesirably change.
The number of hole-electron pairs separated along the track length of the radiation particle, however, is finite, so that the nodal voltage disturbances may be temporary or have only a transient effect. In addition, the density of the radiation particles striking the integrated circuit is generally small enough that the disturbances caused by the radiation particles are treated as single events in time. Such transient disturbances are known as single-event transient (SET) conditions.
After experiencing a SET condition, transistor nodes typically return to their desired voltage states. Consequently, the SET condition might not be a problem in and of itself. The consequence of having a temporary voltage disturbance on the transistor node, however, may be problematic because the SET condition may be propagated through the larger system.
For example, if one of the transistor nodes affected by a radiation particle is in a clock network, then the SET condition can generate a false clock pulse in the clock network portion of the system, thereby throwing off the timing of the larger system. If, for example, one of the transistor nodes affected by a radiation particle is in a data storage element, then the SET condition can flip a storage bit of the data storage element to an opposite state. Consequently, the contents of the data storage element are undesirably changed.
When one of the transistor nodes is in a logic device that feeds data to an input of a latch (or flip-flop, register, etc.), there may or may not be a consequence from the SET condition. For example, if the data recovers to a valid state from a SET condition before the latch closes, it may be of no consequence. If, however, the data does not recover to the valid state before the latch closes, then the wrong data state may be loaded into the latch. In any the above examples and/or other cases where the SET condition propagates through a larger system and causes an undesirable change in the state of the larger system, it may be referred to as a Single-Event Upset (SEU) condition.
SEU conditions can be corrected, and thus, are generally called soft errors. The rate at which the soft errors accumulate is called the soft error rate (SER) and is generally equivalent to the SEU rate. If an integrated circuit has more than one sensitive node (i.e., a node that can change states and cause an SEU condition in response to a radiation particle strike), then the SER for each node is summed to define the total SER for the integrated circuit.
For each sensitive node within an integrated circuit, there is a maximum deposited charge that a transistor or set of transistors (and nodal capacitance) can absorb while maintaining the integrated circuit in a desired state. If a charge induced by a radiation particle exceeds the maximum charge threshold for the transistor and/or set of transistors, a change in the state of the integrated circuit can result. The maximum charge threshold for the most sensitive node or nodes is called the critical charge of the circuit.
To evaluate the SER of a logic circuit, it is necessary to consider the maximum current-carrying capability of its transistors. When a radiation particle traverses a node within the logic circuit, it may force the node from its original state to the opposite state for some period of time. If this node is held in the opposite state for a period longer than a delay to trigger the logic circuit's next stage, then this next stage may undesirably switch states.
The length of time that the node is held in its opposite state may depend on several factors. These factors include the total charge deposited on the node, the conductance of the logic circuit's transistors connected to the node, and the delay between a first stage and second stage of the circuit. One way to reduce the chance of having a SEU condition is to increase the conductance of the transistors, and therefore, increase the size of the transistors. This unfortunately increases the size of logic circuit, which is often undesirable, particularly with data-storage elements that are duplicated many times over.
Another way to reduce the chance of having a SEU condition is to add delay time between the stages of the logic circuit. By increasing the delay, an “ON” transistor is given more time to remove the deposited charge before a voltage-state change can propagate sufficiently through the logic circuit to establish a SET condition, and result in a SEU condition.
The delay can be increased by inserting resistors into the path between stages, such as shown in a cross-coupled data storage circuit in FIG. 1. The cross-coupled resistors have proven effective in increasing the critical charge of a latching-type logic circuit, such as data storage circuit. Thus, the cross-coupled data storage circuit provides some tolerance or immunity to SET and SEU conditions (collectively referred to as Single-Event Effects (“SEE”)). That is, the cross-coupled data storage circuit is to some extent “radiation hardened.” Other equivalent phrases include “radiation hard” or “rad-hard.”
However, because the resistors increase the delay in a data storage circuit feedback loop, the time required to deliberately write the data storage circuit is also increased. To overcome a typical SEU condition, the resistors must be of a size that increases the write time by as much as 5 times the write time of a data storage circuit without the cross-coupled resistors. This is a significant performance penalty.
Another limitation of using cross-coupled resistors is that the material of choice is often polysilicon, often with a sheet resistance of about 100 k-ohm/square. In this region, the temperature coefficient of the polysilicon material is typically large. The temperature coefficient can cause write times to change radically with temperature. As known in the art, such radical changes are undesirable in a stable and reliable system.
In the past, increased write time increases were acceptable, but as the number of logic circuits (and the number of transistors thereof) proliferate, the resulting incremental write time increases are unacceptable from a system perspective. Furthermore, the SERs in these larger systems need to decrease to have a stable and reliable system. Removing the cross-coupled resistors to protect for faster write times will only increase the SERs.
In an alternative approach, the delay in the logic circuit can be increased by inserting cross-coupled transistors, which are turned on during a write operation. A RAM-type data storage circuit having two cross-coupled transistors is shown in FIG. 2. The source of each cross-coupled transistor is connected to the output of one of the data storage circuit inverters. The drain of each cross-coupled transistor is connected to the input of the other one of the data storage circuit inverters. Finally, the gate of each cross-coupled transistor is connected to a word line.
The operation of the cross-coupled transistors is similar to a standard data storage circuit with the following exception. When the word line is high, i.e., the cross-coupled transistors are selected and the resistance of the cross-coupled transistor is low because the transistors are “ON.” Thus, the cell can be written relatively quickly. When the word line is low, the resistance of the cross-coupled transistors is high because the transistors are “OFF.” When the cross-coupled transistors are “OFF,” the critical charge of the data storage circuit is increased, thereby providing some level of radiation hardening.
Unfortunately, the cross-coupled transistors must typically be sufficiently “leaky” when turned “OFF” to function properly. Otherwise the data storage circuit would not remain in its desired state without requiring refresh. To make the cross-coupled transistors sufficiently leaky, a resistive element (see FIGS. 3–4) may be coupled in parallel with the cross-coupled transistors. The resistive element must be large enough to provide the necessary SEU hardness for the data storage circuit. When the data storage circuit is to be written to, the resistive element is shorted out by the cross-coupled transistor.
Another approach is suggested by U.S. Pat. No. 6,058,041; issued on May 2, 2002 and entitled “SEU Hardening Circuit” In U.S. Pat. No. 6,058,041, a SEU hardening circuit consisting of a bypass circuit in the form of a transmission-gate-bypass circuit in parallel with a highly-resistive resistor may be inserted between the first and second stages to reduce the SEE.
This bypass circuit and the previously discussed circuitry, however, may be sensitive to voltage overshoot and/or voltage undershoot conditions. Such overshoot or undershoot conditions can occur, for example, on the input terminal of the SEU hardening circuit as a result of an SET condition upstream from (i.e., before) the bypass circuit. The consequences of such conditions can forward bias a diode and/or turn on one of the transistors in the bypass circuit, thereby undesirably performing the function of bypassing or shorting out the high resistance portion of the circuit. Overshoot and undershoot conditions become more problematic as (i) technology scales down transistor feature sizes, (ii) diode forward bias voltages remain roughly constant, and (iii) transistor turn-on thresholds decrease below diode forward bias voltages. As such, an overshoot or undershoot condition with a magnitude of a forward-bias-diode voltage drop can undesirably turn on the transistors. This, in turn, reduces the logic circuitry's immunity to SEE conditions.
What is needed, therefore, is a system and method that reduces or eliminates the sensitivity to overshoot and undershoot conditions, while increasing the SEE immunity of the circuitry.